1. Field of the Invention
Embodiments of the present invention relate generally to integrated circuit memory read circuits and more specifically to a high-speed single-ended memory read circuit design.
2. Description of the Related Art
Integrated circuits frequently employ various common system building block circuits, such as logic gates and memories blocks, to construct the overall system functionality of a given integrated circuit. Each type of system building block circuit is usually optimized for a given criterion, such as operating speed, power consumption, or die area. Furthermore, architecturally distinct designs may be selected to meet specific optimization criteria. For example, a high-speed memory block that is optimized for operating speed typically incorporates a differential access regime, whereby each memory cell within a storage cell array of memory cells is read and written using a differential pair of bit lines. This differential access regime requires two bit lines per access port, per column of bits. While the differential access regime enables increased operating speed, the additional bit line per access port increases the overall die area of this type of design. Alternately, a high-density memory block that is optimized for die area may use a single-ended access regime, whereby each memory cell within the storage cell array of memory cells is read and written using a single bit line rather then a differential pair of bit lines. While the single-ended access regime requires less die area, the performance of this type of design typically suffers due to performance limitations in conventional single-ended memory read circuits.
High operating speeds are a common requirement in integrated circuits; however, minimizing die area is also an important requirement because die area directly impacts the cost of manufacturing integrated circuits. In certain applications, the smaller die area of a single-ended bit line memory block is highly desirable versus a differential bit line memory block. However, in such applications, the operating speed of a conventional single-ended bit line memory block may not be sufficient due to limitations in conventional single-ended memory read circuits. As a result, differential bit line memory blocks are used instead to satisfy higher operating speed requirements. In these applications, the additional die area required by differential bit line memory blocks results in increased die area and increased overall cost.
As the foregoing illustrates, to optimize speed and die area, what is needed in the art is a high-speed single-ended memory read circuit.